MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 76

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Analog Subsystem
8.3 Analog Control Register
The analog control register (ACR) controls the power-up, interrupt, and flag operation. The analog
subsystem draws current while it is operating. The resulting power consumption can be reduced
by powering down the analog subsystem when not in use (refer to
(V
the ACR at $001D. Since these bits are cleared following a reset, the voltage comparators and the charge
current source will be powered down following a reset of the device.
The control bits in the ACR are shown in
the device.
76
1. Don/t care
VREF
DD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
= 4.5 to 5.5
Analog Multiplex Register
MUX4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Therefore, input voltages cannot be resolved if they are less than the sum
of the AV
a low output from the comparator.
Vdc)). This can be done by clearing three enable bits (ISEN, CP1EN, and CP2EN) in
MUX3
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SS
offset and the comparator offset, because they will always yield
MUX2
Table 8-2. Channel Select Bus Combinations
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MUX1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Figure
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8-5. All the bits in this register are cleared by a reset of
PB4/AN4/
TCMP
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On
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On
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On
Channel Select Bus Connected to:
PB3/AN3/
TCAP
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15.5 Supply Current Characteristics
PB2/AN2
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On
On
Freescale Semiconductor
PB1/AN1
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On
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