MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 68

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Parallel Input/Output
7.4.3 Port C Pulldown Devices
All port C pins can have software programmable pulldown devices enabled or disabled globally by the
SWPDI bit in the MOR. These pulldown devices are individually controlled by the write-only pulldown
register A (PDRA) shown in
controls the lower four pins (PC3–PC0). Clearing the PDICH or PDICL bits in the PDRA turns on the
pulldown devices if the port C pin is an input. Reading the PDRA returns undefined results since it is a
write-only register. Reset clears the PDICH and PDICL bits, which turns on all the port C pulldown
devices.
7.4.4 Port C Logic
Figure 7-15
When a port C pin is programmed as an output, reading the port bit actually reads the value of the data
latch and not the voltage on the pin itself. When a port C pin is programmed as an input, reading the port
bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its
DDR bit.
68
WRITE $0002
WRITE $0006
WRITE $0010
READ $0006
READ $0002
RESET
Table 7-4
shows the I/O logic of port C.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
summarizes the operations of the port C pins.
R
R
PORT C DATA
Figure
REGISTER
BIT PCx
DATA DIRECTION
REGISTER C
BIT DDRCx
REGISTER A
PULLDOWN
BIT PDICx
7-3. PDICH controls the upper four pins (PC7–PC4) and PDICL
Figure 7-15. Port C I/O Circuit
MASK OPTION REGISTER ($1FF1)
Freescale Semiconductor
PULLDOWN
DEVICE
HIGH SINK/SOURCE
CURRENT CAPABILITY
PCx