MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 1172

• Manufacturer Part Number: MC9S12DT256MPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DT256MPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 5 V to 2.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 12KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)
1174
Clock Register
Written
Check
Address, Data,
Access Error and
Protection Violation
Check
Simultaneous
Multiple Flash Block
Decision
Bit Polling for
Command Completion
Check
Command
Buffer Empty Check
Read: FCLKDIV register
Figure 28-26. Example Data Compress Command Flow
1.
2.
3.
yes
Data Compress Signature
Read: FDATA registers
Write: Flash Address to start
compression and number of word
addresses to compress
Write: FCMD register
Data Compress Command 0x06
Write: FSTAT register
Clear CBEIF 0x80
START
FDIVLD
Set?
Read: FSTAT register
Read: FSTAT register
MC9S12XDP512 Data Sheet, Rev. 2.21
yes
ACCERR/
Signature
no
yes
CBEIF
yes
no
Write: FCLKDIV register
Block?
CCIF
Set?
Set?
PVIOL
Set?
Flash
Next
Valid?
EXIT
no
yes
no
yes
no
no
Clear ACCERR/PVIOL 0x30
Write: FSTAT register
by 128K (skip unimplemented Flash)
Decrement Global Address
NOTE: FCLKDIV needs to
be set once after each reset.
Flash Sector(s) Compressed
NOTE: address used to select
Flash block; data ignored.
Erase and Reprogram
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