MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 211

• Manufacturer Part Number: MC9S12DT256MPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DT256MPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 5 V to 2.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 12KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.8.1.8
In this mode the result of an operation between two registers is stored in one of the registers used as
operands.
RD = RD RS is the general register to register format, with register RD being the first operand and RS
the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the
destination register, only the condition code flags are updated. This addressing mode is used only for shift
operations with a variable shift value
Examples:
6.8.1.9
In this mode the result of an operation between two or three registers is stored into a third one.
RD = RS1 RS2 is the general format used in the order RD, RS1, RS1. RD, RS1, RS2 can be any of the
8 general purpose registers R0 … R7. If R0 is used as the destination register RD, only the condition code
flags are updated. This addressing mode is used for all arithmetic and logical operations.
Examples:
6.8.1.10
A 9-bit signed word address offset is included in the instruction word. This addressing mode is used for
conditional branch instructions.
Examples:
6.8.1.11
An 11-bit signed word address offset is included in the instruction word. This addressing mode is used for
the unconditional branch instruction.
Examples:
6.8.1.12
(RS, #offset5) provides an unsigned offset from the base register.
Examples:
Freescale Semiconductor
LSL
LSR
ADC
SUB
BCC
BEQ
BRA
LDB
STW
Dyadic Addressing (DYA)
Triadic Addressing (TRI)
Relative Addressing 9-Bit Wide (REL9)
Relative Addressing 10-Bit Wide (REL10)
Index Register plus Immediate Offset (IDO5)
R4,R5
R4,R5
R5,R6,R7
R5,R6,R7
REL9
REL9
REL10
R4,(R1,#offset)
R4,(R1,#offset)
; R4 = R4 << R5
; R4 = R4 >> R5
MC9S12XDP512 Data Sheet, Rev. 2.21
; R5 = R6 + R7 + Carry
; R5 = R6 - R7
; PC = PC + 2 + (REL9 << 1)
; PC = PC + 2 + (REL9 << 1)
; PC = PC + 2 + (REL10 << 1)
; loads a byte from R1+offset into R4
; stores R4 as a word to R1+offset
Chapter 6 XGATE (S12XGATEV2)
211