MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 794

• Manufacturer Part Number: MC9S12DT256MPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DT256MPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 5 V to 2.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 12KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 21 External Bus Interface (S12XEBIV2)
The following terminology is used:
21.4.2.2.1
796
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
R/W
‘addr’ — value(ADDRx); small letters denote the logic values at the respective pins
‘x’ — Undefined output pin values
‘z’ — Tristate pins
‘?’ — Dependent on previous access (read or write); IVDx: ‘ivd’ or ‘x’; DATAx: ‘data’ or ‘z’
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
R/W
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
R/W
Read Access Timing
...
...
...
...
...
...
...
addr 0
high
?
?
1
Table 21-11. Read Access (n–1 Cycles)
Table 21-10. Read Access (2 Cycles)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 21-9. Read Access (1 Cycle)
iqstat-1
acc 0
low
addr 0
addr 0
?
1
z
z
high
high
?
?
1
?
?
1
1
1
addr 0
iqstat -1
high
iqstat-1
acc 0
acc 0
z
z
1
low
low
Access #0
Access #0
Access #0
?
z
z
1
?
z
z
1
2
iqstat 0
000
low
addr 0
addr 1
data 0
x
z
z
1
high
high
z
1
z
z
1
2
2
addr 0
iqstat 0
iqstat 0
high
acc 1
ivd 0
z
z
1
000
low
low
z
z
1
x
z
z
1
3
0000
000
data 0
low
addr 2
data 1
addr 1
x
z
z
1
high
high
Access #1
Access #1
z
1
z
1
...
...
...
...
...
...
...
...
3
3
Freescale Semiconductor
iqstat 1
acc 2
acc 1
ivd 0
ivd 1
0000
low
low
data 0
addr 1
z
z
1
z
z
1
high
Access #1
z
1
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
n
acc 1
ivd 0
0000
low
z
z
1
...
...
...
...
...
...
...
...