HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 102

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

A basic exception processing sequence consists of the following operations:
4.2.2
The reset vector address is fixed at H'A0000000. The other three events are assigned offsets from
the vector base address by software. Translation lookaside buffer (TLB) miss exceptions have an
offset from the vector base address of H'00000400. The vector address offset for general exception
events other than TLB miss exceptions is H'00000100. The interrupt vector address offset is
H'00000600. The vector base address is loaded into the vector base register (VBR) by software.
The vector base address should reside in P1 or P2 fixed physical address space. Figure 4.1 shows
the relationship between the vector base address, the vector offset, and the vector table.
In table 4.2, exceptions and their vector addresses are listed by exception type, instruction
completion status, relative acceptance priority, relative order of occurrence within an instruction
execution sequence and vector address for exceptions and their vector addresses.
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The contents of the PC and SR are saved in the SPC and SSR, respectively.
The block (BL) bit in SR is set to 1, masking any subsequent exceptions.
The mode (MD) bit in SR is set to 1 to place the SH7708 Series in privileged mode.
The register bank (RB) bit in SR is set to 1.
An encoded value identifying the exception event is written to bits 11–0 of the exception event
(EXPEVT) or interrupt event (INTEVT) register.
Instruction execution jumps to the designated exception processing vector address to invoke
the handler routine.
Exception Handling Vector Addresses
VBR
Figure 4.1 Vector Table
+ Vector offset
H'A000 0000
Vector table