HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 193

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Bit 14: IFC2
0
0
1
1
Note: Do not set the interunal clock frequency lower then the CKIO frequency.
Bits 13, 1 and 0—Peripheral Clock Frequency Division Ratio (PFC): These bits specify the
division ratio of the peripheral clock frequency with respect to the frequency of the output
frequency of PLL circuit 1 or the frequency of the CKIO pin.
Bit 13: PFC2
0
0
1
1
Note: Do not set the peripheral clock frequency higher then the frequency of the CKIO pin.
Bit 8—Clock Enable (CKOEN): Used to output a clock in operating mode 3–6 from the CKIO pin
or to fix the level of the CKIO pin in clock operation modes 3 and 4. Even when the level is fixed,
the SH7708R will operate internally at the frequency before the level was fixed. In case of clock
operating mode 0–2, set this bit to 1. In case of clock operating mode 7, the CKIO pin becomes an
input pin irrespective of the value of this bit.
Bit 8: CKOEN
0
1
Bit 7—PLL Circuit Enable (PLLEN): Specifies the on/off state of PLL circuit 1. This bit is valid
in clock operating modes 3 and 4. PLL circuit 1 goes on when the clock operating mode is 0–2 or
7 irrespective of the value of PLLEN.
Bit 7: PLLEN
0
1
Bit 6—PLL Standby (PSTBY): Specifies PLL standby. When PLL standby is active, PLL circuit 1
will be in standby mode at the frequency specified by the STC bit. This function is valid in clock
operating modes 3 and 4.
Bit 2: IFC1
0
0
0
1
Bit 1: PFC1
0
0
0
1
Description
Fixes the level of CKIO terminal.
Outputs a clock from the CKIO pin.
Description
PLL circuit 1 is not used.
PLL circuit 1 is used.
Bit 1: IFC0
0
1
0
0
Bit 0: PFC0
0
1
0
0
Description
Description
1
1/2
1/3
1/4
1
1/2
1/3
1/4
(Initial value)
(Initial value)
(Initial value)
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