HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 395

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

In receiving, the SCI operates as follows:
1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes
2. Receive data is shifted into SCRSR in order from the LSB to the MSB.
3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR,
Table 13.12 Receive Error Conditions and SCI Operation
Receive Error
Overrun error
Framing error
Parity error
Figure 13.8 shows an example of SCI receive operation in asynchronous mode.
internally and starts receiving.
checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit
c. Status check: RDRF must be 0 so that receive data can be loaded from SCRSR into
the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or
FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCSCR is also set to 1,
the SCI requests a receive-error interrupt (ERI).
setting of the O/E bit in SCSMR.
is checked.
SCRDR.
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in SCRDR. If
one of the checks fails (receive error), the SCI operates as indicated in table 13.12.
Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set
to 1. Be sure to clear the error flags.
Abbreviation
ORER
FER
PER
Condition
Receiving of next data ends while
RDRF is still set to 1 in SCSSR
Stop bit is 0
Parity of receive data differs from
even/odd parity setting in SCSMR
Data Transfer
Receive data not loaded
from SCRSR into SCRDR
Receive data loaded from
SCRSR into SCRDR
Receive data loaded from
SCRSR into SCRDR
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