HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 268

IC SUPERH MPU ROMLESS 144LQFP

HD6417708SF60

Manufacturer Part Number
HD6417708SF60
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417708SF60

Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

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EDO Mode: In DRAM, an extended data out (EDO) mode is also provided in which, once the
CAS signal is asserted while the RAS signal is asserted, even if the CAS signal is negated, data is
output to the data bus until the CAS signal is next asserted. (This is in addition to the mode in
which data is output to the data bus only while the CAS signal is asserted in a data read cycle.) In
the SH7708 Series, the EDO mode bit (EDOMODE) in MCR enables selection, for area 3 DRAM
only, of either normal access/burst access using high-speed page mode or EDO mode normal
access/burst access. EDO mode normal access is shown in figure 10.18, and burst access in figure
10.19.
In EDO mode, the timing for data output to the data bus in a read cycle is extended as far as the
next assertion of the CAS signal. This delays the data latch timing by 1/2 cycle to the rising edge
of the CKIO clock, enabling the DRAM access time to be increased.
248

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