HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 140

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

6.5
The time from generation of an interrupt request until interrupt exception handling is performed
and fetching of the first instruction of the exception handler is started (the interrupt response time)
is shown in table 6.6. Figure 6.4 shows an example of pipeline operation when an IRL interrupt is
accepted. When SR.BL is 1, interrupt exception handling is masked, and is kept waiting until
completion of an instruction that clears BL to 0.
Table 6.6
Item
Time for priority
decision and SR mask
bit comparison
Wait time until end of
sequence being
executed by CPU
Time from interrupt
exception handling
(save of SR and PC)
until fetch of first
instruction of
exception handler is
started
120
Interrupt Response Time
Interrupt Response Time
NMI
0.5
+ 0.5
+ 0.5
X ( 0)
5
Icyc
Icyc
Bcyc
Pcyc
Icyc
Number of States
IRL
0.5
+ 0.5
+ 2
X ( 0)
5
Icyc
Icyc
Pcyc
Bcyc
Icyc
Supporting
Modules
0.5
+ 1.5
X ( 0)
5
Icyc
Icyc
Pcyc
Icyc
Notes
Interrupt exception
handling is kept waiting
until the executing
instruction ends. If the
number of instruction
execution states is S*
the maximum wait time
is:
X = S – 1. However, if
BL is set to 1 by
instruction execution or
by an exception,
interrupt exception
handling is deferred
until completion of an
instruction that clears
BL to 0. If the following
instruction masks
interrupt exception
handling, the handling
may be further deferred.
1
,