HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 200

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Bit 2: CKS2
0
1
Note: If bits CKS2–CKS0 are modified when the WDT is running, the up-count may not be
9.9.3
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers are given
below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction. When writing to
WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 9.5. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the
write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
180
WTCNT write
WTCSR write
Address: H'FFFFFE84
Address: H'FFFFFE86
performed correctly. Ensure that these bits are modified only when the WDT is not running.
Notes on Register Access
Bit 1: CKS1
0
1
0
1
Figure 9.5 Writing to WTCNT and WTCSR
15
15
Bit 0: CKS0
0
1
0
1
0
1
0
1
H'5A
H'A5
Clock Division Ratio
1
1/4
1/16
1/32
1/64
1/256
1/1024
1/4096
(Initial value)
8
8
7
7
Overflow Period
(when P = 15 MHz)
17 s
68 s
273 s
546 s
1.09 ms
4.36 ms
17.46 ms
69.84 ms
Write data
Write data
0
0