HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 424

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Bits 3 to 0: These bits have the same function as in the ordinary SCI. See section 13, Serial
Communication Interface, for more information. The setting conditions for bit 2, the transmit end
bit (TEND), are changed as follows.
Bit 2: TEND
0
1
Note: etu is an abbreviation of elementary time unit, which is the period for the transfer of 1 bit.
14.3
14.3.1
The primary functions of the smart card interface are described below.
1. Each frame consists of 8 data bits and 1 parity bit.
2. During transmission, the card leaves a guard time of at least 2 etu (elementary time units: the
2. During reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed
4. During transmission, it automatically transmits the same data after allowing at least 2 etu from
5. The specification complies with ISO/ICE7816-3, but the only type of data transmission
404
period for 1 bit to transfer) from the end of the parity bit to the start of the next frame.
from the start bit if a parity error was detected.
the time the error signal is sampled.
protocol supported is protocol type T = 0 : asynchronous double-character transmission
protocol.
Operation
Overview
Description
Transmission is in progress.
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE, or when data is written in SCTDR.
End of transmission.
TEND is set to 1 when:
the chip is reset or enters standby mode,
the TE bit in SCSCR is 0 and the FER/ERS bit is also 0,
the C/A bit in SCSMR is 0, and TDRE = 1 and FER/ERS = 0 (normal
transmission) 2.5 etu after a one-byte serial character is transmitted, or
the C/A bit in SCSMR is 1, and TDRE = 1 and FER/ERS = 0 (normal
transmission) 1.0 etu after a one-byte serial character is transmitted.
(Initial value)