HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 102

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Interrupt Controller (INTC)
5.3
5.3.1
The five registers IPRA–IPRE are 16-bit read/write registers that assign priority levels from 0–15
to the IRQ and on-chip supporting module interrupt sources. Interrupt request sources are mapped
onto IPRA–IPRE as shown in table 5.4.
Table 5.4
Register
IPRA
IPRB
IPRC
IPRD
IPRE
Notes: 1. PRT: Parity control unit of bus state controller. See section 8, Bus State Controller
As indicated in table 5.4, four IRQ pins or four groups of on-chip supporting modules are assigned
to each interrupt priority register. The priority levels for the four pins or groups can be set by
setting the corresponding 4-bit groups of bits 15–12, bits 11–8, bits 7–4, and bits 3–0 (of IPRA–
IPRE) with values in the range of H'0 (0000) to H'F (1111). Setting H'0 gives interrupt priority
level 0 (the lowest). Setting H'F gives level 15 (the highest). When two on-chip supporting
modules are assigned to the same bits (DMAC0 and DMAC1, or DMAC2 and DMAC3, or the
parity control unit and the A/D converter, or the watchdog timer and DRAM refresh control unit),
Rev. 7.00 Jan 31, 2006 page 74 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
2. REF: DRAM refresh control unit of bus controller. See section 8, Bus State Controller
3. Always read as 0. Always write 0 in reserved bits.
Register Descriptions
Interrupt Priority Registers A–E (IPRA–IPRE)
(BSC), for details.
(BSC), for details.
Interrupt Request Sources and IPRA-IPRE
Bits 15–12
IRQ0
IRQ4
DMAC0, DMAC1
ITU2
SCI1
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
Bits 11–8
IRQ1
IRQ5
DMAC2, DMAC3
ITU3
PRT *
R/W
R/W
13
0
5
0
1
, A/D
R/W
R/W
12
0
4
0
Bits 7–4
IRQ2
IRQ6
ITU0
ITU4
WDT, REF *
R/W
R/W
11
0
3
0
2
R/W
R/W
10
0
2
0
Bits 3–0
IRQ3
IRQ7
ITU1
SCI0
(Reserved) *
R/W
R/W
9
0
1
0
R/W
R/W
3
8
0
0
0