HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 239

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 2 States + 1 Wait
Figure 9.16 DREQ
Figure 9.17 DREQ
Bus cycle
Bus cycle
Note: When DREQ is negated at the third state of the DMAC cycle, the next DMA
Note: Illustrates the case when DACK is output during the DMAC write cycle.
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States)
DREQ
DREQ
DACK
DACK
CK
CK
transfer will be executed because the sampling is performed at the second state
of the DMAC cycle.
DREQ
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
DREQ
CPU
CPU
CPU
CPU
CPU
CPU
Section 9 Direct Memory Access Controller (DMAC)
State)
DMAC (R) DMAC (W)
T1
DMAC
Tw
T2
Rev. 7.00 Jan 31, 2006 page 211 of 658
CPU
DMAC (W): DMAC write cycle
DMAC (R): DMAC read cycle
CPU
T1
DMAC
Tw
CPU
T2
REJ09B0272-0700
DREQ
DREQ
DREQ Level
DREQ
DREQ
DREQ Level
CPU
CPU

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