HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 212

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Direct Memory Access Controller (DMAC)
9.2
9.2.1
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit read/write registers that specify the
source address of a DMA transfer. During a DMA transfer, these registers indicate the next source
address (in single-address mode, SAR is ignored in transfers from external devices with DACK to
memory-mapped external devices or external memory).
The initial value after a reset or in standby mode is undefined.
9.2.2
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify
the destination address of a DMA transfer. During a DMA transfer, these registers indicate the
next destination address (in single-address mode, DAR is ignored in transfers from memory-
mapped external devices or external memory to external devices with DACK). The initial value
after a reset or in standby mode is undefined.
Rev. 7.00 Jan 31, 2006 page 184 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Register Descriptions
DMA Source Address Registers 0–3 (SAR0–SAR3)
DMA Destination Address Registers 0–3 (DAR0–DAR3)
R/W
R/W
R/W
R/W
31
23
31
23
—
—
—
—
R/W
R/W
R/W
R/W
30
22
30
22
—
—
—
—
R/W
R/W
R/W
R/W
29
21
29
21
—
—
—
—
R/W
R/W
28
28
—
—
R/W
R/W
27
27
—
—
R/W
R/W
26
26
—
…
…
…
…
—
…
…
…
…
R/W
R/W
25
25
—
—
R/W
R/W
R/W
R/W
24
24
—
—
—
—
0
0