HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 387

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 4—Parity Mode (O/E E E E ): O/E selects even or odd parity when parity bits are added and
checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit
(PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in synchronous
mode, or in asynchronous mode when parity addition and checking is disabled.
Bit 4: O/E E E E
0
1
Bit 3—Stop Bit Length (STOP): STOP selects one or two bits as the stop bit length in
asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous
mode because no stop bits are added.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the
next incoming character.
Bit 3: STOP
0
1
Bit 2—Multiprocessor Mode (MP): MP selects multiprocessor format. When multiprocessor
format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The
MP bit setting is used only in asynchronous mode; it is ignored in synchronous mode. For the
multiprocessor communication function, see section 13.3.3, Multiprocessor Communication.
Bit 2: MP
0
1
Description
Even parity
If even parity is selected, the parity bit added to transmit data makes an even
number of 1s in the transmitted character and parity bit combined. Receive
data must have an even number of 1s in the received character and parity bit
combined.
Odd parity
If odd parity is selected, the parity bit added to transmit data makes an odd
number of 1s in the transmitted character and parity bit combined. Receive
data must have an odd number of 1s in the received character and parity bit
combined.
Description
One stop bit
In transmitting, a single 1-bit is added at the end of each transmitted character.
Two stop bits. In transmitting, two 1-bits are added at the end of each
transmitted character.
Description
Multiprocessor function disabled
Multiprocessor format selected
Section 13 Serial Communication Interface (SCI)
Rev. 7.00 Jan 31, 2006 page 359 of 658
REJ09B0272-0700
(Initial value)
(Initial value)
(Initial value)