HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 216

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Direct Memory Access Controller (DMAC)
Bit 7—Acknowledge Mode Bit (AM): In dual address mode, AM selects whether the DACK
signal is output during the data read cycle or write cycle. This bit is valid only in channels 0 and 1.
The AM bit is initialized to 0 by a reset and in standby mode. The AM bit is not valid in single
address mode.
Bit 7: AM
0
1
Bit 6—Acknowledge Level Bit (AL): AL selects active-high or active-low for the DACK signal.
This bit is valid only in channels 0 and 1. The AL bit is initialized to 0 by a reset and in standby
mode.
Bit 6: AL
0
1
Bit 5—DREQ
valid only in channels 0 and 1. The DS bit is initialized to 0 by a reset and in standby mode.
Bit 5: DS
0
1
Bit 4—Transfer Bus Mode Bit (TM): TM selects the bus mode for DMA transfers. The TM bit
is initialized to 0 by a reset and in standby mode. When the source of the transfer request is an on-
chip supporting module, see table 9.4, Selecting On-Chip Peripheral Module Request Modes with
the RS Bits.
Bit 4: TM
0
1
Rev. 7.00 Jan 31, 2006 page 188 of 658
REJ09B0272-0700
DREQ Select Bit (DS): DS selects the DREQ input detection method used. This bit is
DREQ
DREQ
Description
DACK is output in read cycle
DACK is output in write cycle
Description
DACK is active-high
DACK is active-low
Description
DREQ detected by low level
DREQ detected by falling edge
Description
Cycle-steal mode
Burst mode
(Initial value)
(Initial value)
(Initial value)
(Initial value)