HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 237
HD6417032F20V
Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet
1.HD6417034AFI20.pdf
(689 pages)
Specifications of HD6417032F20V
Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
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DREQ pin sampling timing in cycle-steal mode
In cycle-steal mode, the sampling timing is the same regardless of whether DREQ is detected
by edge or level. With edge detection, however, once the signal is sampled it will not be
sampled again until the next edge detection. Once DREQ input is detected, the next sampling
is not performed until the first state, among those DMAC bus cycles thereby produced, in
which a DACK signal is output (including the detection state itself). The next sampling occurs
immediately prior to the rising edge of the clock pulse (CK) of the third state after the bus
cycle previous to the bus cycle in which the DACK signal is output.
Figures 9.13 to 9.22 show the sampling timing of the DREQ pin in cycle-steal mode for each
bus cycle. When no DREQ input is detected at the sampling after the aforementioned DREQ
detection, the next sampling occurs in the next state in which a DACK signal is output. If no
DREQ input is detected at this time, sampling occurs at every subsequent state.
Figure 9.13 DREQ
Bus cycle
DREQ
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 1 State)
DACK
CK
DREQ
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
CPU
CPU
CPU
Section 9 Direct Memory Access Controller (DMAC)
DMAC
Rev. 7.00 Jan 31, 2006 page 209 of 658
CPU
CPU
CPU
REJ09B0272-0700
DREQ
DREQ
DREQ Level
CPU
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