HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 392

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 Serial Communication Interface (SCI)
Bit 7—Transmit Data Register Empty (TDRE): TDRE indicates that the SCI has loaded
transmit data from TDR into TSR and new serial transmit data can be written in TDR.
Bit 7: TDRE
0
1
Bit 6—Receive Data Register Full (RDRF): RDRF indicates that RDR contains received data.
Bit 6: RDRF
0
1
Note: RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit
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REJ09B0272-0700
to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1
when reception of the next data ends, an overrun error (ORER) occurs and the received
data is lost.
Description
TDR contains valid transmit data
TDRE is cleared to 0 when:
TDR does not contain valid transmit data
TDRE is set to 1 when:
Description
RDR does not contain valid received data
RDRF is cleared to 0 when:
RDR contains valid received data.
RDRF is set to 1 when serial data is received normally and transferred from
RSR to RDR.
Software reads TDRE after it has been set to 1, then writes 0 in TDRE
The DMAC writes data in TDR
The chip is reset or enters standby mode
The TE bit in the serial control register (SCR) is cleared to 0
TDR contents are loaded into TSR, so new data can be written in TDR
The chip is reset or enters standby mode
Software reads RDRF after it has been set to 1, then writes 0 in RDRF
The DMAC reads data from RDR
(Initial value)
(Initial value)