HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 193

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Section 8 Bus State Controller (BSC)
8.8
Warp Mode
In warp mode, an external write cycle or DMA single address mode transfer cycle and an internal
access cycle (read/write to on-chip memory or on-chip supporting modules) operate independently
and in parallel. Warp mode is entered by setting the warp mode bit (WARP) in BCR to 1. This
allows the chip to be operated at high speed.
When, in warp mode, an external write cycle or DMA single address mode transfer cycle
continues for at least 2 states and there is an internal access, only the external write cycle will be
performed in the initial state. The external write cycle and internal access cycle will be performed
in parallel from the next state on, without waiting for the end of the external write cycle. Figure
8.34 shows the timing when an access to an on-chip supporting module and an external write cycle
are performed in parallel.
Rev. 7.00 Jan 31, 2006 page 165 of 658
REJ09B0272-0700

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