HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 312

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.4.8
In buffer mode, the buffer operation functions differ depending on whether the general registers
are set to output compare or input capture, reset-synchronized PWM mode, or complementary
PWM mode. Buffer mode is a function of channels 3 and 4 only. Buffer operations set this way
function as follows.
GR is an Output Compare Register: The value of the buffer register of a channel is transferred
to GR when a compare match occurs in the channel. This is illustrated in figure 10.45.
GR is an Input Capture Register: TCNT values are transferred to GR when input capture occurs
and the value previously stored in GR is transferred to BR. This operation is illustrated in figure
10.46.
Complementary PWM Mode: When the count direction of TCNT3 and TCNT4 changes, the BR
value is transferred to GR. The following timing is employed for this transfer:
Rev. 7.00 Jan 31, 2006 page 284 of 658
REJ09B0272-0700
When there is a TCNT3/GRA3 compare-match
When there is a TCNT4 underflows
Input capture signal
Buffer Mode
BR
BR
Figure 10.45 Compare Match Buffer Operation
Figure 10.46 Input Capture Buffer Operation
Compare match signal
GR
GR
Comparator
TCNT
TCNT