HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 213

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.2.3
DMA transfer count registers 0–3 (TCR0–TCR3) are 16-bit read/write registers that specify the
DMA transfer count (bytes or words). The number of transfers is 1 when the setting is H'0001,
65535 when the setting is H'FFFF, and 65536 (the maximum) when H'0000 is set. During a DMA
transfer, these registers indicate the remaining transfer count. The initial value after a reset or in
standby mode is undefined.
9.2.4
DMA channel control registers 0–3 (CHCR0–CHCR3) are 16-bit read/write registers that control
the DMA transfer mode. They also indicate the DMA transfer status. They are initialized to
H'0000 by a reset and in standby mode.
Notes: 1. Only 0 can be written, to clear the flag.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
2. Writing is valid only for CHCR0 and CHCR1.
DMA Transfer Count Registers 0–3 (TCR0–TCR3)
DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
R/(W) *
DM1
R/W
R/W
R/W
AM
15
15
—
—
7
0
7
0
2
R/(W) *
DM0
R/W
R/W
R/W
AL
14
14
—
—
6
0
6
0
2
R/(W) *
SM1
R/W
R/W
R/W
DS
13
13
—
—
5
0
5
0
Section 9 Direct Memory Access Controller (DMAC)
2
SM0
R/W
R/W
R/W
R/W
TM
12
12
—
—
4
0
4
0
Rev. 7.00 Jan 31, 2006 page 185 of 658
R/W
R/W
RS3
R/W
R/W
TS
11
11
—
—
3
0
3
0
R/W
R/W
RS2
R/W
R/W
10
10
—
—
IE
2
0
2
0
REJ09B0272-0700
R/(W) *
R/W
R/W
RS1
R/W
TE
—
—
9
1
9
0
1
0
1
R/W
R/W
RS0
R/W
R/W
DE
—
—
8
0
8
0
0
0