HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 141

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 0—Reserved: This bit is always read as 1. The write value should always be 1.
8.2.3
Wait state control register 2 is a 16-bit read/write register that controls the number of states for
accessing each area with a DMA single address mode transfer and whether wait states are used.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in
standby mode.
Bits 15–8—Wait State Control During Single-Mode DMA Transfer (DRW7–DRW0):
DRW7–DRW0 determine the number of states in single-mode DMA memory read cycles for each
area and whether or not to sample the WAIT signal. Bits DRW7–DRW0 correspond to areas 7–0,
respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the single-mode DMA
memory read cycle for the corresponding area. If it is set to 1, sampling takes place.
For the external memory spaces of areas 1, 3–5, and 7, single-mode DMA memory read cycles are
completed in one state when the corresponding bits are cleared to 0. When they are set to 1, the
number of wait states is 2 plus the wait states from the WAIT signal. For the external memory
space of areas 0, 2, and 6, single-mode DMA memory read cycles are completed in one state plus
the long wait state number (set in wait state controller 3 (WCR3)) when the corresponding bits are
cleared to 0. When they are set to 1, the number of wait states is 1 plus the long wait state; when
the WAIT signal is low as well, a wait state is inserted.
The DRAM space (area 1) finishes the column address output cycle in one state (short pitch) when
the DRW1 bit is 0, and in 2 states plus the wait states from the WAIT signal (long pitch) when
DRW1 is 1. The single-mode DMA memory read cycle of the address/data multiplexed I/O space
(area 6) is 4 states plus the wait states from the WAIT signal, regardless of the setting of the
DRW6 bit.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Wait State Control Register 2 (WCR2)
DWW7
DRW7
R/W
R/W
15
1
7
1
DWW6
DRW6
R/W
R/W
14
1
6
1
DWW5
DRW5
R/W
R/W
13
1
5
1
DWW4
DRW4
R/W
R/W
12
1
4
1
Rev. 7.00 Jan 31, 2006 page 113 of 658
Section 8 Bus State Controller (BSC)
DWW3
DRW3
R/W
R/W
11
1
3
1
DWW2
DRW2
R/W
R/W
10
1
2
1
REJ09B0272-0700
DWW1
DRW1
R/W
R/W
9
1
1
1
DWW0
DRW0
R/W
R/W
8
1
0
1