HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 262

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
10.2
10.2.1
The timer start register (TSTR) is an eight-bit read/write register that starts and stops the timer
counters (TCNT) of channels 0–4. TSTR is initialized to H'E0 or H'60 by a reset and in standby
mode.
Note: * Undefined
Bits 7–5—Reserved: Cannot be modified. Bit 7 is read as undefined. Bits 6 and 5 are always read
as 1. The write value to bit 7 should be 0 or 1, and the write value to bits 6 and 5 should always be
1.
Bit 4—Count Start 4 (STR4): STR4 starts and stops TCNT4.
Bit 4: STR4
0
1
Rev. 7.00 Jan 31, 2006 page 234 of 658
REJ09B0272-0700
Channel Name
4
Bit
Initial value
Read/Write
2. Only 0 can be written to clear flags.
ITU Register Descriptions
Timer Start Register (TSTR)
General register B4
Buffer register A4
Buffer register B4
details on the register addresses, see section 8.3.5, Area Descriptions.
Description
TCNT4 is halted
TCNT4 is counting
7
*
6
1
Abbrevi-
ation
GRB4
BRA4
BRB4
5
1
STR4
R/W
4
0
R/W
R/W
R/W
R/W
STR3
R/W
Initial
Value
H'FF
H'FF
H'FF
3
0
STR2
R/W
2
0
Address *
H'5FFFF3A
H'5FFFF3B
H'5FFFF3C
H'5FFFF3D
H'5FFFF3E
H'5FFFF3F
STR1
R/W
1
0
(Initial value)
1
Access
Size
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
STR0
R/W
0
0

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