HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 496

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Power-Down State
19.4
19.4.1
To enter standby mode, set the standby bit (SBY) to 1 in the standby control register (SBYCR),
then execute the SLEEP instruction. The chip switches from the program execution state to
standby mode. Standby mode greatly reduces power consumption by halting not only the CPU,
but the clock and on-chip supporting modules as well. Some registers of the on-chip supporting
modules are initialized, others are not (See table 19.3). As long as the specified voltage is
supplied, however, CPU register contents and on-chip RAM data are held. The I/O port state (hold
or high impedance) depends on the port high-impedance bit (HIZ) in SBYCR. For details on the
states of these pins, see appendix B, Pin States.
Table 19.3 Register States in Standby Mode
Module
Interrupt controller (INTC)
User break controller (UBC)
Bus state controller (BSC)
Pin function controller (PFC)
I/O ports
Direct memory access
controller (DMAC)
Watchdog timer (WDT)
16-bit integrated timer pulse
unit (ITU)
Programmable timing pattern
controller (TPC)
Serial communication interface
(SCI)
A/D converter (A/D)
Power-down state register
Rev. 7.00 Jan 31, 2006 page 468 of 658
REJ09B0272-0700
Transition to Standby Mode
Standby Mode
Registers Initialized
—
—
—
—
—
All registers
All registers
—
All registers
—
Bits 7–5 (OVF, WT/IT, TME)
in timer control status
register (TCSR)
Reset control/status register
(RSTCSR)
Receive data register (RDR)
Transmit data register (TDR)
Serial mode register (SMR)
Serial control register (SCR)
Serial status register (SSR)
Bit rate register (BBR)
Registers That Hold Data
All registers
All registers
All registers
All registers
All registers
—
—
All registers
—
—
Standby control register
(SBYCR)
Bits 2–0 (CKS2–CKS0) in
timer control status
register (TCSR)
Timer counter (TCNT)