UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 108

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
FFECH to
FFEFH
FFC0H to
FFDFH
FFE0H
FFE1H
FFE2H
FFE3H
FFE4H
FFE5H
FFE6H
FFE7H
FFE8H
FFE9H
FFEAH
FFEBH
FFF0H
FFF1H to
FFFAH
FFFBH
Address
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Note
Remark
IF0
IF1
MK0
MK1
PR0
PR1
IMS
PCC
Symbol
Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value corresponding
to each product as indicated in Table 3-1 after release of reset.
−
−
−
IF0L
IF0H
IF1L
IF1H
MK0L
MK0H
MK1L
MK1H
PR0L
PR0H
PR1L
PR1H
Table 3-8. Special Function Register List: 78K0/KA2-L (25-pin and 32-pin products) (5/5)
For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
<TMIF010> <TMIF000>
<SREIF6> <PIF5> <PIF4> <PIF3> <PIF2>
<TMPR
<SREMK6>
<TMMK
<SREMK6>
RAM2
010>
010>
−
−
−
7
0
0
1
1
1
1
0
<PMK5> <PMK4> <PMK3> <PMK2>
<TMPR
<TMMK
<PPR5> <PPR4> <PPR3> <PPR2>
RAM1
000>
000>
6
−
0
0
1
1
1
1
−
−
0
RAM0
5
−
0
0
0
1
1
1
1
1
−
−
0
1
−
0
1
1
1
1
1
−
0
−
0
4
0
0
1
Bit No.
<TMIF51>
<TMIFH1> <CSIIF10>
<TMMK
<TMMK
ROM3
<TMP
RH1>
<TMP
R51>
H1>
51>
−
−
−
3
0
1
1
0
<CSIPR
<CSIM
ROM2
PCC2
K10
10>
2
−
0
0
0
1
1
1
1
−
−
1
1
<STIF6> <SRIF6>
<PMK0> <LVIMK>
<PIF0> <LVIIF>
<STPR
<STMK
<PPR0> <LVIPR>
ROM1
PCC1
6>
6>
−
−
−
1
0
0
1
1
1
1
<IICAIF0>
<ADIF>
<ADMK>
<SRMK
<SRPR
<ADPR>
<IICAP
ROM0
MK0>
PCC0
<IICA
R0>
6>
6>
−
−
−
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
−
−
−
CHAPTER 3 CPU ARCHITECTURE
−
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
√
1
Simultaneously
Number of Bits
Manipulated
−
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
8
16
−
√
√
√
√
√
√
−
−
−
−
CFH
Reset
After
00H
00H
00H
00H
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
01H
−
−
−
Note
598
598
598
598
606
606
613
613
699
204
606
606
613
613
−
−
−
94