UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 521

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
15.5 I
Figure 15-15 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I
bus’s serial data bus.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that
receives 8-bit data).
level period can be extended and a wait can be inserted.
15.5.1 Start conditions
The start conditions for the SCLA0 pin and SDAA0 pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
been detected (SPD0: Bit 0 of the IICA status register 0 (IICAS0) = 1). When a start condition is detected, bit 1 (STD0) of
the IICAS0 register is set (1).
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The following section describes the I
The master device generates the start condition, slave address, and stop condition.
The serial clock (SCLA0) is continuously output by the master device. However, in the slave device, the SCLA0’s low
A start condition is met when the SCLA0 pin is at high level and the SDAA0 pin changes from high level to low level.
A start condition is output when bit 1 (STT0) of IICA control register 0 (IICACTL0) is set (1) after a stop condition has
2
C Bus Definitions and Control Methods
SDAA0
SCLA0
Start
condition
Figure 15-15. I
Address R/W ACK
1-7
SDAA0
SCLA0
2
C bus’s serial data communication format and the signals used by the I
Figure 15-16. Start Conditions
8
H
2
C Bus Serial Data Transfer Timing
9
Data
1-8
ACK
9
CHAPTER 15 SERIAL INTERFACE IICA
Data
1-8
ACK
9
Stop
condition
2
C bus.
507
2
C