UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 526

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
(IICACTL0).
FFH is written to the IICA shift register (IICA), and the transmitting side cancels the wait state when data is written to the
IICA register.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(2) When master and slave devices both have a nine-clock wait
Remark
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of the IICA control register 0
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of the IICACTL0 register is set to 1 or when
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of IICACTL0 register to 1
• By setting bit 0 (SPT0) of IICACTL0 register to 1
Transfer lines
(master transmits, slave receives, and ACKE0 = 1)
Master
Slave
ACKE0: Bit 2 of IICA control register 0 (IICACTL0)
WREL0: Bit 5 of IICA control register 0 (IICACTL0)
ACKE0
SDAA0
SCLA0
SCLA0
SCLA0
IICA
IICA
H
Generate according to previously set ACKE0 value
D2
6
6
Master and slave both wait
after output of ninth clock
D1
7
7
D0
8
8
Figure 15-21. Wait (2/2)
ACK
9
9
Wait from
master and
slave
Wait from slave
IICA data write (cancel wait)
1
CHAPTER 15 SERIAL INTERFACE IICA
D7
1
FFH is written to IICA or WREL0 is set to 1
D6
2
2
D5
3
3
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