UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 527

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
15.5.7 Canceling wait
register 0 (IICACTL0) to 1.
value may be output to SDAA0 line because the timing for changing the SDAA0 line conflicts with the timing for writing the
IICA register.
aborted, so that the wait state can be canceled.
IICACTL0 register, so that the wait state can be canceled.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The I
• Writing data to IICA shift register (IICA)
• Setting bit 5 (WREL0) of IICA control register 0 (IICACTL0) (canceling wait)
• Setting bit 1 (STT0) of IICACTL0 register (generating start condition)
• Setting bit 0 (SPT0) of IICACTL0 register (generating stop condition)
When the above wait canceling processing is executed, the I
To cancel a wait state and transmit data (including addresses), write the data to the IICA register.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IICA control
To generate a restart condition after canceling a wait state, set bit 1 (STT0) of the IICACTL0 register to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of the IICACTL0 register to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to the IICA register after canceling a wait state by setting the WREL0 bit to 1, an incorrect
In addition to the above, communication is stopped if the IICE0 bit is cleared to 0 when communication has been
If the I
Caution If a processing to cancel a wait state executed when WUP (bit 7 of the IICA control register 1
Note Master only
2
C usually cancels a wait state by the following processing.
2
C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of the
(IICACTL1)) = 1, the wait state will not be canceled.
2
C cancels the wait state and communication is resumed.
Note
Note
CHAPTER 15 SERIAL INTERFACE IICA
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