UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 71

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
<R>
78K0/Kx2-L
Notes 1.
Cautions 1. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 are set in the analog
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
P00/TI000
P01/TO00/TI010
P10/ANI8/ANP1-
P11/ANI9/ANP1OUT
P12/ANI10/ANP1+
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
ANI0/P20/AMP0-
ANI1/P21/AMP0OUT
PGAIN
ANI2/P22/AMP0+
ANI3/P23
P30/INTP1
P31/INTP2/TOOLC1
P32/INTP3/TOOLD1
P33/TI51/TO51/INTP4
P60/SCLA0/INTP11
P61/SDAA0/INTP10
P120/EXLVI/INTP0
P121/X1/TOOLC0
P122/X2/EXCLK/TOOLD0
RESET/P125
AV
AV
REF
SS
Note 1
2. If this pin is left open when specified as an analog input pin, the input voltage level might become undefined. It
3. Use recommended connection above in input port mode (refer to Figure 5-3 Format of Clock Operation
4. When port 2 is used as the digital port pins, make AV
Pin Name
2. Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset
μ
is therefore recommended to leave this pin open after specifying it as a digital output pin.
Mode Select Register (OSCCTL)) when these pins are not used.
PD78F0576, 78F0577, and 78F0578 (products with operational amplifier) only
input mode, P10/ANI8/AMP1-/SCK10, P11/ANI9/AMP1OUT/SI10, and P12/ANI10/AMP1+/SO10 are set
in the digital input mode after release of reset.
signal is generated during low level input, the reset status continues until the input rises to the high
level.
Note 1
Note 1
Note 1
Note 3
Note 1
/SCK10
Note 1
Note 1
/SO10
/SI10
/
Note 3
5-AQ
11-L
11-M
11-K
5-AG
5-AQ
5-AG
5-AQ
11-P
11-O
11-N
11-G
5-AQ
5-AS
5-AQ
37-A
42-A
I/O Circuit Type
Table 2-5. Pin I/O Circuit Types (78K0/KB2-L)
−
−
I/O
Input
Input
I/O
−
−
Input:
Output: Leave open.
<Digital input setting>
Independently connect to AV
<Digital output setting and analog input setting>
Leave open.
Input:
Output: Leave open.
Input:
Output: Leave this pin open at low-level output after clearing
Independently connect to V
Connect directly to V
Connect directly to V
Connect directly to V
REF
Independently connect to V
Independently connect to V
Independently connect to V
the output latch of the port to 0.
the same potential as V
Recommended Connection of Unused Pins
Note 2
DD
DD
SS
.
.
or via a resistor.
Note 4
DD
REF
or V
CHAPTER 2 PIN FUNCTIONS
or AV
SS
DD
DD
DD
via a resistor.
DD
SS
.
or V
or V
or V
via a resistor.
SS
SS
SS
via a resistor.
via a resistor.
via a resistor.
57