UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 259

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Operation as interval timer
Operation as square-wave output
Operation as external event counter
Operation in the clear & start mode
entered by TI000 pin valid edge input
Operation as free-running timer
Operation as PPG output
Operation as one-shot pulse output
Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output is
(i) When CR010 is used as a compare register
(ii) When CR010 is used as a capture register
(iii) Setting range when CR000 or CR010 is used as a compare register
The value set in CR010 is constantly compared with the TM00 count value, and an interrupt request signal
(INTTM010) is generated if they match.
Caution CR010 does not perform the capture operation when it is set in the comparison mode, even if a
The count value of TM00 is captured to CR010 when a capture trigger is input.
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 pin valid edge is set by
PRM00.
When CR000 or CR010 is used as a compare register, set it as shown below.
not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the timer
counter (TM00 register) is changed from 0000H to 0001H.
• When the timer counter is cleared due to overflow
• When the timer counter is cleared due to TI000 pin valid edge (when clear & start mode is entered by TI000
• When the timer counter is cleared due to compare match (when clear & start mode is entered by match
pin valid edge input)
between TM00 and CR000 (CR000 = other than 0000H, CR010 = 0000H))
Address: FF14H, FF15H
CR010
Operation
capture trigger is input to it.
Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
15
14
13
12
After reset: 0000H
FF15H
0000H < N ≤ FFFFH
0000H
M < N ≤ FFFFH
0000H
CR000 Register Setting Range
11
Note
Note
10
≤ N ≤ FFFFH
≤ N ≤ FFFFH (N ≠ M)
9
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
R/W
8
7
6
0000H
Normally, this setting is not used. Mask the
match interrupt signal (INTTM010).
0000H
0000H
0000H
5
4
FF14H
Note
Note
Note
Note
CR010 Register Setting Range
≤ M ≤ FFFFH
≤ M ≤ FFFFH
≤ M < N
≤ M ≤ FFFFH (M ≠ N)
3
2
1
0
245