UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 642

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
(5) Program status word (PSW)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The program status word is a register used to hold the instruction execution result and the current status for an
interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple
interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the
contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request
is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP
flag. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the
stack with the RETI, RETB, and POP PSW instructions.
Reset signal generation sets PSW to 02H.
PSW
<7>
IE
<6>
Z
RBS1
<5>
<4>
AC
Figure 17-24. Format of Program Status Word
RBS0
<3>
2
0
<1>
ISP
CY
0
ISP
IE
0
1
0
1
Used when normal instruction is executed
After reset
02H
High-priority interrupt servicing (low-priority
interrupt disabled)
Interrupt request not acknowledged, or low-
priority interrupt servicing (all maskable
interrupts enabled)
Disabled
Enabled
Interrupt request acknowledgment enable/disable
Priority of interrupt currently being serviced
CHAPTER 17 INTERRUPT FUNCTIONS
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