UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 413

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
11.3 Registers Controlling Clock Output Controller
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The following two registers are used to control the clock output controller.
• Clock output selection register (CKS)
• Port mode register 4 (PM4)
(1) Clock output selection register (CKS)
Notes 1.
Caution Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
This register sets output enable/disable for clock output (PCL) and sets the output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears CKS to 00H.
Address: FF40H
Symbol
CKS
Figure 11-2. Format of Clock Output Selection Register (CKS) (48-pin products of 78K0/KC2-L)
2.
If the peripheral hardware clock (f
operating frequency varies depending on the supply voltage.
• V
• V
If internal high-speed oscillation clock frequency is set to 8 MHz (R4M8MSEL = 0) by option byte and the
peripheral hardware clock (f
1.8 V ≤ V
DD
DD
= 2.7 to 5.5 V: f
= 1.8 to 2.7 V: f
CLOE
CCS3
7
0
0
1
0
0
0
0
0
0
0
0
1
DD
After reset: 00H
< 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: f
Clock division circuit operation stopped. PCL fixed to low level.
Clock division circuit operation enabled. PCL output enabled.
CCS2
Other than above
6
0
0
0
0
0
1
1
1
1
0
PRS
PRS
≤ 10 MHz
≤ 5 MHz
R/W
PRS
CCS1
) operates on the internal high-speed oscillation clock (f
5
0
0
0
1
1
0
0
1
1
0
PRS
) operates on the high-speed system clock (f
PCL output enable/disable specification
CLOE
CCS0
<4>
0
1
0
1
0
1
0
1
0
CHAPTER 11 CLOCK OUTPUT CONTROLLER
f
f
f
f
f
f
f
f
f
Setting prohibited
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
SUB
CCS3
Note 2
/2
/2
/2
/2
/2
/2
/2
3
2
3
4
5
6
7
32.768 kHz
32.768 kHz
PCL output clock selection
f
SUB
−
CCS2
=
2
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
4 MHz
f
PRS
CCS1
=
1
XH
) (XSEL = 1), the f
−
Note 1
PRS
IH
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
156.25 kHz
78.125 kHz
) (XSEL = 0) when
10 MHz
) is prohibited.
f
CCS0
PRS
0
=
399
PRS