UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 528

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
15.5.8 Interrupt request (INTIICA0) generation timing and wait control
generated and the corresponding wait control, as shown in Table 15-2.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The setting of bit 3 (WTIM0) of IICA control register 0 (IICACTL0) determines the timing by which INTIICA0 is
Notes 1. The slave device’s INTIICA0 signal and wait period occurs at the falling edge of the ninth clock only when
Remark
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
(4) Wait cancellation method
WTIM0
• Slave device operation:
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
The four wait cancellation methods are as follows.
• Writing data to IICA shift register (IICA)
• Setting bit 5 (WREL0) of IICA control register 0 (IICACTL0) (canceling wait)
• Setting bit 1 (STT0) of IICACTL0 register (generating start condition)
• Setting bit 0 (SPT0) of IICACTL0 register (generating stop condition)
When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
0
1
Note Master only.
2. If the received address does not match the contents of the slave address register 0 (SVA0) and extension
there is a match with the address set to the slave address register 0 (SVA0).
At this point, ACK is generated regardless of the value set to bit 2 (ACKE0) of the IICACTL0 register. For a
slave device that has received an extension code, INTIICA0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIICA0 is generated at the falling edge of the 9th
clock, but wait does not occur.
code is not received, neither INTIICA0 nor a wait occurs.
The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and wait
control are both synchronized with the falling edge of these clock signals.
Address
9
9
Notes 1, 2
Notes 1, 2
During Slave Device Operation
Table 15-2. INTIICA0 Generation Timing and Wait Control
Data Reception
Notes 1 and 2 above, regardless of the WTIM0 bit.
WTIM0 bit.
Interrupt and wait timing are determined depending on the conditions described in
8
9
Note 2
Note 2
Data Transmission
8
9
Note 2
Note 2
Address
CHAPTER 15 SERIAL INTERFACE IICA
9
9
Note
Note
During Master Device Operation
Data Reception
8
9
Data Transmission
8
9
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