UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 462
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
TMRmn
TOMm
TOEm
TOLm
TOm
(a) Timer mode register mn (TMRmn)
(b) Timer output register m (TOm)
(c) Timer output enable register m (TOEm)
(d) Timer output level register m (TOLm)
(e) Timer output mode register m (TOMm)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
TOMmn
TOEmn
CKSmn
TOLmn
TOmn
Bit n
Bit n
Bit n
Bit n
1/0
15
0
0
0
0
Figure 8-55. Example of Set Contents of Registers to Measure Input Pulse Interval
78K0R/KF3-L, 78K0R/KG3-L:
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin):
78K0R/KD3-L, 78K0R/KE3-L:
Operation clock selection
14
0
0: Outputs 0 from TOmn.
0: Stops TOmn output operation by counting operation.
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0: Sets master channel output mode.
13
0
CCSmn
12
0
Count clock selection
TERmn
MAS
11
0: Selects operation clock.
0
Slave/master selection
STSmn2
10
0: Independent channel operation function.
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
0
STSmn1
9
0
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07
mn = 00 to 07, 10 to 13
Capture trigger selection
STSmn0
001B: Selects the TImn pin input valid edge.
8
1
CISmn1
1/0
7
CISmn0
1/0
6
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Operation mode of channel n
010B: Capture mode
5
0
Setting of operation when counting is started
CHAPTER 8 TIMER ARRAY UNIT
0: Does not generate INTTMmn when
1: Generates INTTMmn when counting is
counting is started.
started.
4
0
MDmn3
3
0
MDmn2
2
1
MDmn1
1
0
MDmn0
1/0
0
462
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