UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 541
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0).
Remarks 1. n = 0:
Note
Address: FFFA5H (CKS0), FFFA6H (CKS1)
Symbol
CKSn
Use the output clock within a range of 10 MHz. Furthermore, when using the output clock at V
it within 5 MHz.
2. To shift to STOP mode when the main system clock is selected (CSELn = 0), set PCLOEn = 0
2. f
3. f
before executing the STOP instruction. When the subsystem clock is selected (CSELn = 1),
PCLOEn = 1 can be set because the clock can be output in STOP mode.
n = 0, 1: 78K0R/KE3-L, 78K0R/KF3-L, 78K0R/KG3-L
MAIN
SUB
PCLOEn
PCLOEn
CSELn
: Subsystem clock frequency
: Main system clock frequency
<7>
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 11-2. Format of Clock Output Select Register n (CKSn)
78K0R/KC3-L (48-pin), 78K0R/KD3-L
Output disable (default)
Output enable
CCSn2
6
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
CCSn1
5
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
After reset: 00H
PCLBUZn pin output enable/disable specification
CCSn0
4
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
CSELn
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
3
2
3
4
5
6
7
2
3
4
11
12
13
PCLBUZn pin output clock selection
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
2.44 kHz
1.22 kHz
610 Hz
5 MHz
f
MAIN
CCSn2
=
2
5 MHz
2.5 MHz
625 kHz
4.88 kHz
2.44 kHz
1.22 kHz
10 MHz
1.25 MHz
32.768 kHz
16.384 kHz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
10 MHz
512 Hz
256 Hz
f
MAIN
CCSn1
Note
1
=
Setting
prohibited
10 MHz
5 MHz
2.5 MHz
1.25 MHz
9.76 kHz
4.88 kHz
2.44 kHz
20 MHz
f
CCSn0
MAIN
DD
0
Note
< 2.7 V, use
=
Note
541
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