UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 793
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
SDA0
SCL0
Figure 15-25 shows the communication reservation timing.
Remark
Communication reservations are accepted via the timing shown in Figure 15-26. After bit 1 (STD) of the IICA
status register (IICS) is set to 1, a communication reservation can be made by setting bit 1 (STT) of IICA control
register 0 (IICCTL0) to 1 before a stop condition is detected.
Figure 15-27 shows the communication reservation protocol.
SDA0
SCL0
SPD
STD
Hardware processing
Program processing
1
IICA:
STT:
STD:
SPD:
2
Standby mode (Communication can be reserved by setting STT to 1 during this period.)
3
Figure 15-26. Timing for Accepting Communication Reservations
IICA shift register
Bit 1 of IICA control register 0 (IICCTL0)
Bit 1 of IICA status register (IICS)
Bit 0 of IICA status register (IICS)
Communi-
cation
reservation
STT = 1
4
Figure 15-25. Communication Reservation Timing
5
6
7
Generate by master device with bus mastership
8
9
Set SPD
and
INTIICA
CHAPTER 15 SERIAL INTERFACE IICA
Write to
IICA
Set
STD
1
2
3
4
5
6
793
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