UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 866
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
17.5.5 Forced termination by software
bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn)
of DMAn, therefore, perform either of the following processes.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn
<When using one DMA channel>
• Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software, confirm by polling
• Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software and then set the
<When using both DMA channels>
• To forcibly terminate DMA transfer by software when using both DMA channels (by setting DSTn to 0), clear the
Remarks 1. n: DMA channel number (n = 0, 1)
that the DSTn bit has actually been cleared to 0, and then set the DENn bit to 0 (use DRCn = 00H to write with an 8-
bit manipulation instruction).
DENn bit to 0 (use DRCn = 00H to write with an 8-bit manipulation instruction) two or more clocks after.
DSTn bit to 0 after the DMA transfer is held pending by setting the DWAIT0 and DWAIT1 bits of both channels to 1.
Next, clear the DWAIT0 and DWAIT1 bits of both channels to 0 to cancel the pending status, and then clear the
DENn bit to 0.
2. 1 clock: 1/f
Example 1
DSTn = 0 ?
DENn = 0
DSTn = 0
Yes
CLK
Figure 17-11. Forced Termination of DMA Transfer (1/2)
(f
CLK
: CPU clock)
No
Example 2
2 clock wait
DENn = 0
DSTn = 0
CHAPTER 17 DMA CONTROLLER
866
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