UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 543
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 543 of 1171
- Download datasheet (8Mb)
78K0R/Kx3-L
11.4 Operations of Clock Output/Buzzer Output Controller
11.4.1 Operation as output pin
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
One pin can be used to output a clock or buzzer sound.
The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
The PCLBUZ1 pin outputs a clock/buzzer selected by the clock output select register 1 (CKS1).
The PCLBUZn pin is output as the following procedure.
<1> Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register (CKSn)
<2> Set bit 7 (PCLOEn) of the CKSn register to 1 to enable clock/buzzer output.
Remarks 1. The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
of the PCLBUZn pin (output in disabled status).
Clock output
2. n = 0:
disabling clock output (PCLOEn bit) is switched. At this time, pulses with a narrow width are not output.
Figure 11-4 shows enabling or stopping output using the PCLOEn bit and the timing of outputting the clock.
n = 0, 1: 78K0R/KE3-L, 78K0R/KF3-L, 78K0R/KG3-L
PCLOEn
Narrow pulses are not recognized
78K0R/KC3-L (48-pin), 78K0R/KD3-L
Figure 11-4. Remote Control Output Application Example
1 clock elapsed
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
543
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