UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 965
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
25.1.2 On-chip debug option byte (000C3H/ 010C3H)
25.2 Format of User Option Byte
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: 000C0H/010C0H
The format of user option byte is shown below.
Caution Set the same value as 000C3H to 010C3H when the boot swap operation is used because
Control of on-chip debug operation
• On-chip debug operation is disabled or enabled.
Handling of data of flash memory in case of failure in on-chip debug security ID authentication
• Data of flash memory is erased or not erased in case of failure in on-chip debug security ID
authentication.
WINDOW1
WDTINIT
WDTINIT
WDTON
WDCS2
7
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
1
000C3H is replaced by 010C3H.
Note 1
Interval interrupt is not used.
Interval interrupt is generated when 75% of the overflow time is reached.
Counter operation disabled (counting stopped after reset)
Counter operation enabled (counting started after reset)
Figure 25-1. Format of User Option Byte (000C0H/010C0H) (1/2)
WINDOW1
WINDOW0
WDCS1
6
0
1
0
1
0
0
1
1
0
0
1
1
Setting prohibited
50%
75%
100%
WINDOW0
WDCS0
5
0
1
0
1
0
1
0
1
Operation control of watchdog timer counter
Use of interval interrupt of watchdog timer
2
2
2
2
2
2
2
2
7
8
9
10
12
14
15
17
WDTON
/f
/f
/f
/f
/f
/f
/f
/f
IL
IL
IL
IL
IL
IL
IL
IL
(3.71 ms)
(7.42 ms)
(14.84 ms)
4
(29.68 ms)
(118.72 ms)
(474.90 ms)
(949.80 ms)
(3799.19m s)
Watchdog timer window open period
WDCS2
3
Watchdog timer overflow time
(f
IL
= 34.5 kHz (MAX.))
WDCS1
2
CHAPTER 25 OPTION BYTE
Note 2
WDCS0
1
WDSTBYON
0
965
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