UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 830
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(3) Data ~ data ~ Stop condition
Notes 1. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during master transmission.
(communication status)
(communication status)
(8 or 9 clock wait)
(8 or 9 clock wait)
(wait cancellation)
(wait cancellation)
(transmit/receive)
(transmit/receive)
(ACK detection)
(ACK detection)
Master side
(ST detection)
(SP detection)
(ACK control)
(ACK control)
Slave side
(SP trigger)
SDA0 (bus)
(ST trigger)
SCL0 (bus)
(clock line)
Bus line
(interrupt)
(data line)
(interrupt)
2. Make sure that the time between the rise of the SCL0 pin signal and the generation of the stop condition
3. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
INTIICA
INTIICA
WTIM
MSTS
MSTS
WTIM
WREL
WREL
ACKD
ACKE
ACKD
ACKE
TRC
STD
SPD
TRC
IICA
STT
SPT
IICA
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4)
after a stop condition has been issued is at least 4.0
μ
s when specifying fast mode.
D
H
H
L
L
15
<7>
L
H
H
L
L
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
0
Figure 15-32. Example of Master to Slave Communication
ACK
Note 1
<9>
<8>
<10>
D
16
Note 3
7
D
16
6
D
16
5
D
16
4
Stop condition
D
16
μ
3
s when specifying standard mode and at least 0.6
CHAPTER 15 SERIAL INTERFACE IICA
D
16
2
D
16
1
D
<11>
16
0
<12>
ACK
<13>
<14>
Note 2
Note 3
<15>
830
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