UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 860
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
trigger.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The fist trigger for consecutive transmission is not started by the interrupt of CSI. In this example, it start by a software
CSI transmission of the second time and onward is automatically executed.
A DMA interrupt (INTDMA0) occurs when the last transmit data has been written to the data register.
Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA0 (INTDMA0), set the DST0 bit to 0 and then the DEN0 bit to 0 (for details,
refer to 17.5.5 Forced termination by software).
Setting for CSI transfer
Figure 17-7. Example of Setting for CSI Consecutive Transmission
DRA0 = FB00H
DBC0 = 0100H
DMC0 = 48H
User program
DSA0 = 44H
processing
DEN0 = 1
STG0 = 1
DST0 = 1
Occurrence of
INTDMA0
Start
DST0 = 0
DEN0 = 0
DMA is started.
INTCSI10 occurs.
RETI
End
Note
DMA0 transfer
transmission
CSI
CHAPTER 17 DMA CONTROLLER
Hardware operation
860
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