HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 1005

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

SMR1—Serial Mode Register 1
Bit
Initial value
Read/Write
Note:
GSM mode
0 Normal smart card interface mode operation
1
:
:
:
• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
• Clock output on/off control only
GSM mode smart card interface mode operation
• TEND flag generation 11.0 etu after beginning of start bit
• High/low fixing control possible in addition to clock output on/off control (set by SCR)
etu: Elementary Time Unit (time for transfer of 1 bit)
R/W
GM
7
0
Block transfer mode
0 Normal smart card interface mode operation
1
• Error signal transmission/detection and automatic data retransmission performed
• TXI interrupt generated by TEND flag
• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)
Block transfer mode operation
• Error signal transmission/detection and automatic data retransmission not performed
• TXI interrupt generated by TDRE flag
• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)
R/W
BLK
6
0
Note: When the smart card interface is used, be sure to make the 1 setting.
Parity enable
0 Parity bit addition and checking disabled
1
Parity bit addition and checking enabled
R/W
PE
5
0
Parity mode
Notes: 1. When even parity is set, parity bit addition is performed in
0 Even parity
1
Odd parity
2. When odd parity is set, parity bit addition is performed in
R/W
O/E
transmission so that the total number of 1 bits in the transmit
character plus the parity bit is even.
In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is even.
transmission so that the total number of 1 bits in the transmit
character plus the parity bit is odd.
In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is odd.
4
0
*2
*1
H'FF80
Rev. 5.00 Jan 10, 2006 page 979 of 1042
BCP1
R/W
3
0
Basic clock pulse
0
1
Appendix B Internal I/O Register
0 32 clock periods
1
0
1
BCP0
64 clock periods
372 clock periods
256 clock periods
R/W
2
0
Smart Card Interface
CKS1
R/W
1
0
REJ09B0275-0500
Clock select
0
1
0
1
0
1
CKS0
/4 clock
/16 clock
/64 clock
R/W
clock
0
0