HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 1013

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

SMR2—Serial Mode Register 2
Bit
Initial value
Read/Write
Asynchronous mode/synchronous mode select
0 Asynchronous mode
1
Synchronous mode
:
:
:
Character length
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
0 8-bit data
1
R/W
7-bit data*
C/A
7
0
Parity enable
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the
0 Parity bit addition and checking disabled
1
CHR
R/W
Parity bit addition and checking enabled *
6
0
O/E bit is added to transmit data before transmission. In reception, the
parity bit is checked for the parity (even or odd) specified by the O/E bit.
R/W
Notes: 1. When even parity is set, parity bit addition is performed
Parity mode
PE
0 Even parity
1
5
0
Odd parity
2. When odd parity is set, parity bit addition is performed
R/W
in transmission so that the total number of 1 bits in the
transmit character plus the parity bit is even.
In reception, a check is performed to see if the total
number of 1 bits in the receive character plus the parity
bit is even.
in transmission so that the total number of 1 bits in the
transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total
number of 1 bits in the receive character plus the parity
bit is odd.
O/E
4
0
*2
*1
H'FF88
Rev. 5.00 Jan 10, 2006 page 987 of 1042
STOP
Stop bit length
R/W
0 1 stop bit
1
3
0
2 stop bits
Multiprocessor mode
0 Multiprocessor function disabled
1
Appendix B Internal I/O Register
Multiprocessor format selected
R/W
MP
2
0
CKS1
R/W
Clock select
1
0
0
1
REJ09B0275-0500
0
1
0
1
/4 clock
/16 clock
/64 clock
CKS0
clock
R/W
0
0
SCI