HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 488

IC H8S MCU FLASH 256K 100-QFP

HD64F2623FA20J

Manufacturer Part Number
HD64F2623FA20J
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2623FA20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 13 Serial Communication Interface (SCI)
Table 13.11 Receive Errors and Conditions for Occurrence
Receive Error
Overrun error
Framing error
Parity error
Figure 13.8 shows an example of the operation for reception in asynchronous mode.
Rev. 5.00 Jan 10, 2006 page 462 of 1042
REJ09B0275-0500
RDRF
FER
1
Start
bit
0
D0
Abbreviation
ORER
FER
PER
Figure 13.8 Example of SCI Operation in Reception
D1
(Example with 8-Bit Data, Parity, One Stop Bit)
1 frame
Data
D7
Occurrence Condition
When the next data reception
is completed while the RDRF
flag in SSR is set to 1
When the stop bit is 0
When the received data differs
from the parity (even or odd)
set in SMR
RXI interrupt
request
generated
Parity
bit
0/1
Stop
bit
1
Start
bit
0
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
D0
D1
Data
Receive data is not
transferred from RSR to
RDR.
Receive data is transferred
from RSR to RDR.
Receive data is transferred
from RSR to RDR.
Data Transfer
D7
Parity
bit
ERI interrupt request
generated by framing
error
0/1
Stop
bit
0
Idle state
(mark state)
1

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