HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 307

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Port F Data Register (PFDR)
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).
PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Bit 7 in PFDR is reserved, and only 0 may be written to it.
Port F Register (PORTF)
Note:
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as
PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes
the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input
port.
Mode 7
Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in
the case of pin PF7, the output pin. Clearing the bit to 0 makes the pin an input port.
* Determined by state of pins PF7 to PF0.
:
:
:
:
R/W
PF7
—*
—
R
7
0
7
PF6DR
R/W
PF6
—*
R
6
0
6
PF5DR
R/W
PF5
—*
R
5
0
5
PF4DR
R/W
PF4
—*
R
4
0
4
Rev. 5.00 Jan 10, 2006 page 281 of 1042
PF3DR
R/W
PF3
—*
R
3
0
3
PF2DR
R/W
PF2
—*
R
2
0
2
Section 9 I/O Ports
PF1DR
REJ09B0275-0500
R/W
PF1
—*
R
1
0
1
PF0DR
R/W
PF0
—*
R
0
0
0