L6460 STMicroelectronics, L6460 Datasheet - Page 36

• Manufacturer Part Number: L6460
• Description: MOSFET & Power Driver ICs SPI Config Stepper DC Multi Motor DRV
• Manufacturer: STMicroelectronics
• Type: Full-Bridge Driverr

Specifications of L6460

• Product: Half-Bridge Drivers
• Rise Time: 0.4 us
• Fall Time: 0.4 us
• Supply Voltage (max): 38 V
• Supply Voltage (min): 13 V
• Supply Current: 11 mA
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 4
• Output Current: 10 mA
• Output Voltage: 30 V
• Package / Case: TQFP-64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Watchdog circuit
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Watchdog circuit
The Watchdog timer can be used to reset L6460 if it is not serviced by the firmware that can
periodically write at logic level “1’ the ClrWDog bit in the WatchDogStatus register.
This circuit is disabled by default; firmware can enable it by setting at logic level ‘1’ the
WDEnable bit in the WatchDogCfg register.
When the Watchdog timeout event happens, L6460 sets to ‘1’ a latched bit WDTimeOut in
theWatchDogStatus register that can be read using SPI interface; once this bit is set it can
be cleared in three ways:
The Watchdog function includes also a warning bit WDWarning to indicate, via serial
interface or via the circuit called Interrupt Controller (see
near to its timeout; this bit is asserted to logic level “1” exactly one watch dog clock period
(WD_Tclk) before the watchdog timeout happens. Firmware can enable the WDTimeOut
signal to cause an “nRst_int” event by setting to logic ‘1’ the WDEnnRst bit.
Figure 6.
The watchdog timeout has an imprecision of maximum one WD_Tclk. The effective
programmed WD time is changed in the register only when the watchdog circuit is serviced
by firmware with ClrWDog bit. At this time the watchdog timer is reset and the new value of
the WD delay value is loaded.
The watchdog timer can be programmed to generate different timeouts using the
WDdelay[3:0] bits in the WatchDogCfg register according to following table.
–
–
–
by writing a ‘1’ in the WDClear bit in the WatchDogStatus register.
by writing a ‘1’ in the SoftReset bit in the WatchDogStatus register.
by a POR event.
Fosc
Watchdog circuit block diagram
Frequency divider
Doc ID 17713 Rev 1
WD_clk Watchdog counter
To SPI
Chapter
generation circuit
To nRSTint
21) that the watchdog is
L6460