ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 118

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

12.12.6
118
ATtiny261A/461A/861A
PLLCSR – PLL Control and Status Register
the Output Compare Override Enable Bit is cleared.
Override Enable Bits and their corresponding Output Compare pins.
Table 12-22. Output Compare Override Enable Bits vs. Output Compare Pins
• Bit 7- LSM: Low Speed Mode
The Low Speed mode is set, if the LSM bit is written to one. Then the fast peripheral clock is
scaled down to 32 MHz. The Low Speed Mode must be set, if the supply voltage is below 2.7
volts, because the Timer/Counter1 is not running fast enough on low voltage levels. It is recom-
mended that the Timer/Counter1 is stopped whenever the LSM bit is changed.
Note, that LSM can not be set if PLL
• Bit 6:3- Res : Reserved Bits
These bits are reserved and always read zero.
• Bit 2- PCKE: PCK Enable
The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock
mode is enabled and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as a
Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and
system clock CK is used as Timer/Counter1 clock source. It is safe to set this bit only when the
PLL is locked i.e the PLOCK bit is 1. Note that the PCKE bit can be set only, if the PLL has been
enabled earlier. The PLL is enabled when the CKSEL fuse has been programmed to 0x0001
(the PLL clock mode is selected) or the PLLE bit has been set to one.
• Bit 1- PLLE: PLL Enable
When the PLLE is set, the PLL is started and if needed internal oscillator is started as a PLL ref-
erence clock. If PLL is selected as a system clock source the value for this bit is always 1.
• Bit 0- PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be
ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots,
before reaching steady state. The steady state is obtained within 100 µs. After PLL lock-in it is
recommended to check the PLOCK bit before enabling PCK for Timer/Counter1.
Bit
0x29 (0x49)
Read/Write
Initial value
Output CompareOverride Enable Bit
OC1OE0
OC1OE1
OC1OE2
OC1OE3
OC1OE4
OC1OE5
7
LSM
R/W
0
6
-
R
0
5
-
R
0
CLK
Output Compare Output
OC1A
OC1A
OC1B
OC1B
OC1D
OC1D
is used as a system clock.
4
-
R
0
3
-
R
0
Table 12-22
2
PCKE
R/W
0
shows the Output Compare
PB0
PB1
PB2
PB3
PB4
PB5
Output Compare Pin
1
PLLE
R/W
0/1
0
PLOCK
R
0
8197B–AVR–01/10
PLLCSR