ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 42

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

8.2.4
8.3
8.3.1
8.4
42
Internal Voltage Reference
Watchdog Timer
ATtiny261A/461A/861A
Watchdog Reset
Voltage Reference Enable Signals and Start-up Time
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
“Watchdog Timer” on page 42
Figure 8-6.
ATtiny261A/461A/861A features an internal bandgap reference. This reference is used for
Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The
bandgap voltage varies with supply voltage and temperature, as can be seen in
page
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
reference is not always turned on. The reference is on during the following situations:
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
8-3 on page
Watchdog Timer is also reset when it is disabled and when a device reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the device resets and executes from the Reset Vector. For
timing details on the Watchdog Reset, refer to
1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuse bits).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
217.
ACBG bit in ACSR).
CC
47. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
Watchdog Reset During Operation
“System and Reset Characteristics” on page
for details on operation of the Watchdog Timer.
CK
Table 8-3 on page
47.
187. To save power, the
Figure 20-45 on
8197B–AVR–01/10
TOUT
. Refer to
Table