ATTINY861A-SU Atmel, ATTINY861A-SU Datasheet - Page 84

• Manufacturer Part Number: ATTINY861A-SU
• Description: IC, MCU, 8BIT, 8K FLASH, 20SOIC
• Manufacturer: Atmel

Specifications of ATTINY861A-SU

• Controller Family/series: ATtiny
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

11.10.4
11.10.5
11.10.6
11.10.7
84
ATtiny261A/461A/861A
TCNT0H – Timer/Counter0 Register High Byte
OCR0A – Timer/Counter0 Output Compare Register A
OCR0B – Timer/Counter0 Output Compare Register B
TIMSK – Timer/Counter0 Interrupt Mask Register
When 16-bit mode is selected (the TCW0 bit is set to one) the Timer/Counter Register TCNT0H
combined to the Timer/Counter Register TCNT0L gives direct access, both for read and write
operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes
are read and written simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by
all the other 16-bit registers. See
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0L). A match can be used to generate an Output Compare interrupt.
In 16-bit mode the OCR0A register contains the low byte of the 16-bit Output Compare Register.
To ensure that both the high and the low bytes are written simultaneously when the CPU writes
to these registers, the access is performed using an 8-bit temporary high byte register (TEMP).
This temporary register is shared by all the other 16-bit registers. See
16-bit Mode” on page
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0L in 8-bit mode and TCNTH in 16-bit mode). A match can be used to gen-
erate an Output Compare interrupt.
In 16-bit mode the OCR0B register contains the high byte of the 16-bit Output Compare Regis-
ter. To ensure that both the high and the low bytes are written simultaneously when the CPU
writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
isters in 16-bit Mode” on page
• Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
Bit
0x14 (0x34)
Read/Write
Initial Value
Bit
0x13 (0x33)
Read/Write
Initial Value
Bit
0x12 (0x32)
Read/Write
Initial Value
Bit
0x39 (0x59)
Read/Write
Initial Value
OCIE1D
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
78.
OCIE1A
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
78.
OCIE1B
“Accessing Registers in 16-bit Mode” on page 78
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
OCIE0A
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
TCNT0H[7:0]
OCR0A[7:0]
OCR0B[7:0]
OCIE0B
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
TOIE1
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
TOIE0
R/W
R/W
R/W
R/W
“Accessing Registers in
1
0
1
0
1
0
1
0
TICIE0
“Accessing Reg-
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
8197B–AVR–01/10
TCNT0H
OCR0A
OCR0B
TIMSK